`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:04:20 04/17/2014
// Design Name:   Vigenere
// Module Name:   C:/Users/rpobrien/Documents/School/cis6930-network-security/SBoxCipher/SBoxDecrypt/Vigenere_ICN_tb.v
// Project Name:  SBoxCipher
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Vigenere
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Vigenere_ICN_tb;

	// Inputs
	reg [127:0] key;
	reg [127:0] data_in;
	reg clk;

	// Outputs
	wire [127:0] data_out;
	wire [127:0] icn_in;

	// Instantiate the Unit Under Test (UUT)
	Vigenere vig (
		.key(key), 
		.data_in(data_in), 
		.data_out(icn_in), 
		.clk(clk)
	);
	
	Omega_3x8 ICN (
		.data_in(icn_in),
		.data_out(data_out),
		.sel(key[23:0])
		);

	always #5 clk = ~clk;

	initial begin
		// Initialize Inputs
		key = 0;
		data_in = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		data_in = "hello guys. this";
		key = "AAAAAAAAAAAAAAAA";
		#10;
		$display("IN:\t%s", data_in);
		$display("OUT:\t%s", data_out);
        
		// Add stimulus here

	end
      
endmodule

